The invention relates to accommodating different components.
Processors for Desktop/Server platforms are available from a variety of manufacturers such as Intel, Analog Micro Devices ("AMD"), Cyrix, and NexGen. While all processors are designed to operate in essentially the same environment, each manufacturer designs its processors to be somewhat different than those of the other manufacturers. In addition, each manufacturer periodically upgrades its processor families, releasing products that differ from those previously offered by that manufacturer.
The computer system manufacturer that wishes to use several types of computer processors or to provide its customers with available processor upgrades must accommodate the differences between the processors. Typically, this requires the computer manufacturer to develop and maintain a distinct hardware design (e.g., printed circuit card) for each processor it wishes to accommodate. When a processor upgrade becomes available, instead of simply substituting the upgraded processor for the obsolete processor, the computer manufacturer must provide an upgraded processor card. As a result, both the computer manufacturer and its customers must incur significant expense to keep up with processor improvements.
Referring to FIG. 1A, the typical computer includes a processor 20 which has internal primary cache memory (not shown) and which is connected to secondary cache memory 22 via a system bus 24. Referring to FIG. 1B, some newer processors, such as Intel's Pentium Pro processor, include secondary cache 22 in the same package 16, and the CPU communicates with secondary cache 22 using a private internal bus 18.
FIGS. 1A and 1B are block diagrams of conventional computer system components. The NexGen Nx586 and H86 processors are connected to secondary cache through a dedicated bus (not shown) that services only the processor and the secondary cache. Secondary cache memories typically have sizes of 128K bytes, 256K bytes, or 512K bytes, but may have other values in certain applications.
The processor 20 is driven by a system clock 26, (bus clock) which typically oscillates at a frequency between 50 MHz and 66 MHz. However, today's processors usually operate at core frequencies much greater than the standard bus clock speeds, with core speeds typically varying from 100 MHz to more than 200 MHz. As a result, the processor 20 must multiply the bus clock frequency to attain a higher core speed. For example, a 150 MHz processor running from a 60 MHz bus clock (i.e., a bus/core ratio of 2/5) must multiply the bus clock frequency by a factor of 5/2. The computer system not only provides the bus clock 26 to the processor 20, but typically it also supplies the value of the frequency multiplier to the processor through a multi-bit input signal 28 to ensure that the processor operates at the proper speed.
The processor 20 interacts with memory 21 through a memory data path 23 and a memory interface buffer 25. A memory data controller 27 manages the flow of data through the memory device 21 and the memory interface buffer 25. The processor 20 also may access the system's PCI bus 29 through a PCI bridge 31. The PCI bus 29 is connected to the system's ISA/EISA bus 33 through a PCI/EISA bridge 35.
Each processor is designed to operate at a specific primary core voltage V.sub.CCP. The core voltage may vary not only between processor families but also between processors of the same family, including processors that otherwise appear to be the same. For example, Intel's P6.0 150 MHz processor is targeted to operate at a core voltage of 3.1 volts. However, down-binned processors that do not meet this requirement may still be rated at 150 MHz for a higher core voltage, e.g., 3.3 volts. Or a processor targeted to operate with a core speed of 180 MHz at 3.3 volts may fail to meet this requirement, but may satisfy a down-binned requirement of 150 MHz at a core voltage of only 3.1 volts. As a result, the computer manufacturer often must maintain several hardware designs even for a single processor type.
Referring to FIG. 2, Intel has included on each Pentium Pro processor package four voltage identification (VID) pins. The VID pins provide four bits 30 of binary data that indicate the designed core voltage setting V.sub.CCP 32 for that processor. The VID bits 30, which are hardwired to a particular value when the processor is packaged, identify a core voltage setting that is correct only if the processor actually operates at the designed voltage V.sub.CCP (i.e., the processor is not down-binned).
Referring now to FIG. 3, many processors implement a bus interface technology known as gunning transceiver logic (GTL).* In a GTL system, a processor 34 and other components 36, 38 having open drain I/O ports are linked in daisy-chain fashion by a bus 40, each end of which must be pulled to a termination voltage V.sub.TT by pull-up resistors 42, 44. If either of the pull-up resistors 42, 44 is missing, the GTL system will not operate properly. Similar pull-up resistors are required for every signal line connecting the processor 34 and the other system components 36, 38. Thus, for a 160-signal bus, 320 pull-up resistors are needed. FNT *JEDEC Standard JESD8-3: Gunning Transceiver Logic (GTL) Low-Level, High-Speed Interface Standard for digital Interface Circuits.
Under the GTL standard, the termination voltage V.sub.TT has a value of 1.2 volts. HIGH and LOW level logic signals are determined by a reference voltage V.sub.REF, which by definition has a value equal to 2/3 V.sub.TT, or 0.8 volts. However, because this value of V.sub.REF is so close to typical noise levels, a digital standard known as GTL.sup.+ was created to provide greater noise margin. Under the GTL.sup.+ standard, the termination voltage V.sub.TT is 1.5 volts and the reference voltage V.sub.REF, which equals 2/3 V.sub.TT, is 1.0 volts.